Method and device for the incremention of counter statuses stored in memory cells of a memory
US8064567B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Sep 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/102
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for the incrementation of counter statuses in memory cells, which are arranged respectively in rows and columns of a first memory adds a “1” to the memory content of a memory cell of a second memory, which corresponds to the memory cell at the start of a sequence of memory cells to be incremented in a row or column of the first memory in the case of every incrementation of a sequence of memory cells of the first memory, and adds a “−1” to the memory content of a memory cell of the second memory, which corresponds to the memory cell immediately following the memory cell at the end of the sequence of memory cells to be incremented associated with the start of the sequence, in the case of every incrementation of a sequence of memory cells of the first memory. It then recursively adds the memory content of a memory cell arranged in a row or column of the second memory to the memory content of the memory cell arranged in the next lower row or column of the first memory and stores the result of the addition in the memory cell arranged in the row or column of the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.