Soft error detection logic testing systems and methods
US8065574B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jan 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.