Patent · US Active

Fault tolerant integrated circuit architecture

US8067954B2 · kind B2 · utility

2Cited by
2References
67Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 7, 2010
Grant dateNov 29, 2011
Priority date
Expiry dateMar 7, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K19/17764
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.