Programmable delay line compensated for process, voltage, and temperature
US8067959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2010 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.