Input surge protection device using JFET
US8068321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2008 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | May 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H7/1213
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An input surge suppression device and method that uses a simple JFET structure. The JFET has its gate clamped to a predetermined value, its the drain receives the input voltage from an input power source, its source is connected to the input of a down-stream device, and a resistor connected between the drain and the gate or between the source and the gate. Thus, when the drain voltage approximates the clamped gate voltage, the source voltage nearly equals the drain voltage. When the drain voltage rises above the clamped gate voltage, the source voltage is lower than the drain voltage. The downstream device may be a DC-DC converter and the gate is biased by the enable (EN) pin of a DC-DC converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.