Hardware support for instruction set emulation
US8069023B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2008 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Mar 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.