Method and apparatus for processing financial information at hardware speeds using FPGA devices

US8069102B2 · kind B2 · utility

Assignee

• Washington University · US

Inventors

• Ronald S. Indeck · Chesterfield, US
• Ron K. Cytron · Chesterfield, US
• Mark Allen Franklin · Chesterfield, US
• Roger D. Chamberlain · Chesterfield, US

Key dates

• Filing date: Nov 20, 2006
• Grant date: Nov 29, 2011
• Expiry date: Nov 7, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S707/99936
• WIPO field: IT methods for management
• WIPO sector: Electrical engineering

Abstract

A method and apparatus use decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.