Internally triggered reconfiguration of programmable logic devices
US8069329B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2008 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.