Patent · US Active

Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal

US8069363B2 · kind B2 · utility

11Cited by

22References

6Claims

0Family size

Assignee

Mosaid Technologies Incorporated · CA

Inventors

Alan Roth · Austin, US
Oswald Becca · Round Rock, US
Pedro Ovalle · Austin, US

Key dates

Filing date	Aug 19, 2009
Grant date	Nov 29, 2011
Priority date	—
Expiry date	Dec 23, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F5/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.