Method of ONO integration into MOS flow
US8071453B1 · kind B1 · utility
46Cited by
1References
24Claims
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Key dates
| Filing date | Oct 29, 2009 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.