Semiconductor memory device and method for manufacturing same
US8071969B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2009 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Nov 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
Abstract
A semiconductor memory device includes a word line interconnect layer having a plurality of word lines extending in a word line direction and a bit line interconnect layer having a plurality of bit lines extending in a bit line direction alternately stacked on a silicon substrate. A variable resistance film is disposed between the word line and the bit line. A first pin diode extending in the word line direction is provided between the word line and the variable resistance film, and a second pin diode extending in the bit line direction is provided between the bit line and the variable resistance film. A region of an upper surface of the pin diode other than an immediately underlying region of the variable resistance film is located lower than the immediately underlying region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.