Double-gated sensor cell

US8072006B1 · kind B1 · utility

Assignee

• American Semiconductor, Inc. · US

Inventors

• Douglas R. Hackler, Sr. · Boise, US
• Richard A. Hayhurst · Nampa, US
• Stephen A. Parke · Nampa, US

Key dates

• Filing date: Dec 21, 2005
• Grant date: Dec 6, 2011
• Expiry date: Sep 8, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/014

Abstract

A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.