Nonvolatile semiconductor memory device
US8072020B2 · kind B2 · utility
0Cited by
9References
19Claims
0Family size
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Key dates
| Filing date | Mar 27, 2009 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
Abstract
A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.