Nonvolatile semiconductor memory device

US8072021B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kenji Gomikawa · Yokohama, JP
• Tadashi Iguchi · Yokkaichi, JP
• Mitsuhiro Noguchi · Yokohama, JP
• Shoichi Watanabe · Fukushima, JP

Key dates

• Filing date: Aug 8, 2008
• Grant date: Dec 6, 2011
• Expiry date: Oct 6, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.