Memory with five-transistor bit cells and associated control circuit
US8072796B2 · kind B2 · utility
1Cited by
18References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Apr 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.