Patent · US Active

Synchronous de-skew with programmable latency for multi-lane high speed serial interface

US8073090B2 · kind B2 · utility

14Cited by

2References

20Claims

0Family size

Assignee

Integrated Device Technology, Inc. · US

Inventors

Liang Zhang · Shanghai, CN
Hui Wang · Irvine, US
Yong Wang · Shanghai, CN

Key dates

Filing date	Jul 11, 2008
Grant date	Dec 6, 2011
Priority date	—
Expiry date	May 10, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/14
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.