Method for implementing montgomery modular multiplication and device therefore
US8073891B2 · kind B2 · utility
2Cited by
3References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Sep 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Device for implementing modular multiplication, characterized in that it comprises at least one computation cell comprising a multiplier-adder comprising p pipelined logic-register pairs, receiving several digits to be added together and multiplied, at least two outputs corresponding to the low order and to the high order, an adder receiving the two outputs of the multiplier-adder, the number p being chosen in such a way that the maximum frequency of the multiplier-adder is greater than or equal to the maximum frequency of the adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.