Compact switched-capacitor FIR filter implementation
US8073894B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2007 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Sep 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H19/004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system is provided to perform non-recursive signal processing tasks using a sampled data technique and a network of switched-capacitor filters. The input analog signal is sampled in a time sequence manner at regular time intervals in order to obtain analog-valued samples. These samples are collected into data blocks and the data blocks are assembled into a set of data blocks. The successive data blocks belonging to a set of data blocks partially overlap with the first data block. The non-recursive signal processing is performed on all of the data blocks of the set substantially simultaneously, using a parallel network of switched capacitor filters, in order to produce a processed analog output signal. Each individual processing path of the parallel network of switched capacitor filters processes a specific data block of the set of data blocks. The number of parallel processing paths is the same as one plus the degree of the polynomial representing the desired or overall input/output equation characterizing the non-recursive signal processing. An implementing architecture can be simplified by factorizing the polynomial representing the input/output equation into smaller sized poly…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.