Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8074055B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1999 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Aug 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.