Integrated circuit design systems for replacing flip-flops with pulsed latches
US8074190B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2010 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Apr 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.