Lead plating technique for singulated IC packages

US8076181B1 · kind B1 · utility

Assignee

• Linear Technology Holding LLC · US

Inventors

• David Alan Pruitt · San Jose, US
• Lothar Maier · Tüßling, DE

Key dates

• Filing date: Oct 22, 2010
• Grant date: Dec 13, 2011
• Expiry date: Oct 22, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.