Digital phase-locked loop with two-point modulation using an accumulator and a phase-to-digital converter
US8076960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.