Array substrate and display panel having the same
US8077269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Jul 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136218
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes; a thin-film transistor layer including; a gate line, a data line disposed substantially perpendicular to the gate line, and a switching element connected to the gate line and the data line, a gate insulation layer disposed on the gate line, a passivation layer disposed on the thin-film transistor layer, a shielding electrode disposed on the passivation layer, an insulation layer disposed on the shielding electrode; and a pixel electrode including a micro-slit pattern, the pixel electrode being disposed on the insulation layer and electrically connected to the switching element, wherein the shielding electrode is vertically aligned with the data line and the shielding electrode blocks an electromagnetic fringe field of the data line from effecting the pixel electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.