E/P durability by using a sub-range of a full programming range
US8077518B2 · kind B2 · utility
2Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2011 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Jan 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.