Nonvolatile semiconductor memory device
US8077525B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being configured by an assembly of NAND cell units, each of the NAND cell units including a plurality of nonvolatile memory cells connected in series and word lines configured to commonly connect control gates of the memory cells. A data erase operation is executed by first applying a pre-charge voltage to the word lines, then setting to a floating state the word lines in a non-selected block where erasure of data is not to be executed, applying a certain voltage to the word lines in a selected block where erasure of data is to be executed and applying an erase voltage to a well where the memory cell array is formed, thereby altering a threshold voltage of the memory cells in the selected block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.