Signal routing in processor arrays
US8077623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Nov 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the method comprising (i) identifying a signal from the plurality of unrouted signals to route; (ii) identifying a candidate route from the source processor element to the destination processor element, the candidate route using a first plurality of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal to be routed through the first plurality of switches; and (iv) attempting to route the signal using one of the offset values identified in step (iii).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.