System and method of controlling power consumption in a digital phase locked loop (DPLL)
US8077822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Oct 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.