Pipelined processing of RDMA-type network transactions
US8078743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/1097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed. If the work request gets ahead of the MR OP, the associated pending bit being set will n…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.