Scaleable array of micro-engines for waveform processing
US8078829B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2007 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Oct 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.