Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US8078833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Oct 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.