Reconfigurable array processor for floating-point operations
US8078835B2 · kind B2 · utility
8Cited by
5References
31Claims
0Family size
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Key dates
| Filing date | May 23, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Mar 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.