Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to stored messages in an internal register
US8078838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Mar 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first and second processors. The multiport semiconductor memory device includes a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator. The first processor is coupled to the at least one shared memory area via the first port, the second processor is coupled to the at least one shared memory area via the second port, and the wake-up signal generator is coupled to the first processor and the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.