Parsing-enhancement facility using a translate-and-test instruction
US8078841B2 · kind B2 · utility
6Cited by
11References
22Claims
0Family size
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Key dates
| Filing date | Apr 3, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Jan 31, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.