Detecting memory-hazard conflicts during vector processing
US8078847B2 · kind B2 · utility
27Cited by
22References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Sep 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when memory operations are performed in parallel using at least a portion of the vectors, and tracking positions in at least one of the vectors of any detected conflict between the memory addresses. Next, the processor executes the instructions for detecting the conflict between the memory addresses and tracking the positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.