Patent · US Active

Method and system for performing pattern classification of patterns in integrated circuit designs

US8079005B2 · kind B2 · utility

21Cited by

4References

29Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ya-Chieh Lai · Mountain View, US
Frank E. Gennari · Berkeley, US
Matthew W. Moskewicz · Berkeley, US
Junjiang Lei · Fremont, US
Weinong Lai · Fremont, US

Key dates

Filing date	Sep 30, 2008
Grant date	Dec 13, 2011
Priority date	—
Expiry date	Mar 12, 2030

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed is an approach for performing pattern classification for electronic designs. One advantage of this approach is that it can use fast pattern matching techniques to classify both patterns and markers based on geometric similarity. In this way, the large number of markers and hotspots that typically are identified within an electronic design can be subsumed and compressed into a much smaller set of pattern families. This significantly reduced the number of patterns that must be individually analyzed, which considerably reduces the quantity of system resources and time needed to analyze and verify a circuit design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.