Method for fabricating semiconductor device with increased breakdown voltage
US8080455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Mar 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
Abstract
A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.