Differential source follower source leader addressable node readout circuit
US8080775B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A readout circuit for reading from addressable nodes comprises first and second half-circuits of a differential amplifier. The first half-circuit comprises at least one source follower transistor adapted to receive an input signal from one of the addressable nodes, such as pixel readouts of an imaging system. The first half-circuit further comprises a row selector switch coupled to the source follower transistor to selectively activate the source follower transistor to receive the input signal. The second half-circuit comprises an output node for providing an output signal of a readout of a selected addressable node. The second half-circuit further comprises a source leader transistor coupled to the output node to provide a feedback signal based on the readout. A feedback loop is connected to the source leader transistor to provide feedback from the output node for utilization in a differential amplification of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.