Clock signal frequency dividing circuit and clock signal frequency dividing method
US8081017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2007 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.