Multilayer chip capacitor
US8081416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2008 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Sep 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/232
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.