Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method
US8081522B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14v-1 including a bit line selector 14s, a page buffer unit circuit 14u including two latch L1, L2, and a latch L3 is set up for a plurality of bit lines. The bit line selector 14s selects one bit line and couples it to the page buffer unit circuit 14u. The latch L1 temporally stores the data which are read out from the memory cell of the selected bit line, and then outputs the data through the latch L2 or L3. On the other hand, the latch L1 temporally stores the programming data inputted through the latch L2 or L3, and after that outputs it to the memory cell of the selected bit line for programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.