Circuit for memory module
US8081536B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2011 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Feb 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.