Semiconductor integrated circuit manufacturing process evaluation method
US8082536B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
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Key dates
| Filing date | Mar 20, 2009 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.