Method of manufacturing semiconductor device
US8084352B2 · kind B2 · utility
14Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Mar 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process can be used to provide a driving circuit and a data line driver which make it possible to improve resistance to possible noise occurring between adjacent terminals, while controlling a chip size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.