Gate minimization threshold voltage of FET for synchronous rectification
US8084823B2 · kind B2 · utility
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12Claims
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Inventor
Key dates
| Filing date | Oct 26, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Oct 26, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.