Overclocking with phase selection
US8085070B2 · kind B2 · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.