Differentially compensated input pair
US8085093B2 · kind B2 · utility
0Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Dec 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45244
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention is directed to an amplifier including an absolute value circuit. The absolute value circuit may be driven by differential potentials and may include a first pair of transistors modulating a tail current of the amplifier when a differential input voltage goes high, and a second pair of transistors modulating the tail current of the amplifier when a differential input voltage goes low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.