Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters
US8085176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2011 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Mar 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/424
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.