Integrated capacitor arrangement for ultrahigh capacitance values
US8085524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2006 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Dec 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
Abstract
An electronic device includes at least one trench capacitor that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence of at least two dielectric layers and at least two electrically conductive layers is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. A range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.