Hardware driven processor state storage prior to entering a low power
US8086883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Mar 28, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus includes a processor for processing data and having memory interface logic for controlling transfer of data to a memory. Also included is a memory for storing data processed by said processor. The processor is powered in a first domain and the memory is powered in a second domain. A system bus is coupled to the processor and the memory to transfer data therebetween in response to memory transfer requests. The processor is responsive to a low power request to enter a low power mode to control transfer of state data indicating a current state of the processor to the memory via the system bus using memory interface logic. The state data is sufficient to restore the processor to an equivalent program state following exit from the low power mode, store the state data in memory; and power down the first domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.