Design Structure for switching digital circuit clock net driver without losing clock pulses
US8086977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | May 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.